The present invention relates in general to DC power supply circuits and components therefor, and is particularly directed to a high resolution digital diode emulator (DDE) for a DC-DC converter. At each inductor current (IL) cycle, a digital counter counts a high frequency clock signal from the turn-off time of the gate of a first pass element of the converter""s output switching circuit until the gate of a second pass element is turned off. The contents of the digital counter are latched in memory, and incremented or decremented at the next IL cycle depending upon whether diode emulation has occurred in the current cycle too early or too late. The gate of a second pass element is turned off when the contents of the counter match the modified latch count.
FIG. 1 diagrammatically illustrates the general circuit configuration of a conventional DC-DC voltage converter as comprising a DC-DC controller 10, which switchably controls the turn-on and turn-off of a pair of electronic power -switching devices, respectively shown as an upper FET pass element 20 and a lower FET pass element 30. These FET switching devices have their drain-source paths coupled in series between first and second reference voltages (VDD and ground (GND)). Each Pass element contains a controllable switch shown as an upper switch 22 and a lower switch 32. The upper pass element contains a body diode 21 in parallel with the drain-source path such that the reverse current flows through the body diode toward VDD. The lower pass element 30 contains a body diode 31 in parallel with the drain-source path such that reverse current flows through the body diode from GND. A common or phase voltage node 25 between the two power FETs 20/30 is coupled through an inductor 40 to a capacitor 50 coupled to a reference voltage terminal (GND). The connection 45 between the inductor 40 and the capacitor 50 serves as an output node from which an output voltage VOUT is derived.
The DC-DC converter""s controller 10 includes a gate driver circuit 11, that is operative to controllably turn the two switching devices 20 and 30 on and off, in accordance with a periodic pulse signal waveform (typically, a pulse width modulation (PWM) switching waveform such as that shown at PWM in the timing diagram of FIG. 2) generated by a (PWM) logic circuit 12. The upper switch 22 is turned on and off by an upper gate switching signal UG applied by the gate driver 11 to the gate of the pass element 20, and the lower switch 32 is turned on and off by a lower gate switching signal LG applied by the gate driver 11 to the gate of the pass element 30.
For the case of the timing diagram of FIG. 2, the upper switch 22 is turned on in accordance with the rising edge of the PWM waveform and turned off in accordance with the falling edge of the PWM waveform, whereas the lower switch 32 is turned on in accordance with the falling edge of the PWM waveform. During relatively light load conditions, where the ripple current IL through the inductor 40 is larger than the average inductor current, it is desired to revert to a basic DC-DC converter. This is effected by effectively replacing the lower switch 32 with a diode function optimally turning off the lower switching device coincident with the negative-going zero-crossing of the inductor ripple current. IL, so as to prevent current return flow back into the converter, and maximizing efficiency.
Prior art techniques to accomplish this diode transition operation may sense the ripple current flowing through the inductor 40 via node 45, or may sense the phase voltage at node 25 and couple the sensed variation to a comparator. FIG. 1 shows the example where the phase node voltage VPH is coupled to a comparator 13. Ideally, the comparator, which is enabled by the PWM logic circuit, will provide an output coincident with the negative-going, zero-crossing of the ripple current, in response to which the controller""s output driver turns off the lower switch.
Unfortunately, this technique is successful only at relatively low PWM frequencies, due to the propagation delay through the comparator. To obtain reasonably acceptable performance at relatively high PWM frequencies (e.g., on the order of 1 MHZ and above), it is necessary to use a comparator that requires a large bias current, which increases cost and is not practical for low power applications. This technique is also susceptible to errors due to noise caused by the switching power devices.
In accordance with the present invention, shortcomings of conventional DC-DC converter diode emulators, including those described above, are effectively obviated by means of a high resolution digital diode emulator (DDE), which monitors the converter""s phase voltage node, and employs a high frequency clock and a digital counter. For each periodic signal cycle (such as a PWM cycle), or a pulse frequency modulation (PFM), the digital counter counts high frequency clock signals beginning with the turn-off time of a first pass element of the converter""s output switching circuit until its second pass element is turned off.
The contents of the digital counter are latched in a count memory, whose contents are incremented or decremented at the next cycle, depending upon whether diode emulation has occurred too early or too late. When the control loop begins operating in diode emulation mode, the count memory will have been pre-loaded with the maximum digital count that can be reached by the digital counter. This serves to prevent premature generation of the lower switch turn-off signal. Once the DDE begins cycling, the count memory will then be successively loaded with the contents of the digital counter, in response to respective load signals for sequential cycles of the periodic signal.
Although the lower switch turn-off signal is not expected to occur at the exact moment that the inductor current becomes zero amps, it will be close. Where an inductor current cycle""s turn-off signal to the power switching circuit""s lower switch occurs too late, which allows the inductor current to go below zero amps, the negative inductor current flows through the upper pass element""s body diode causing the phase voltage to quickly increase toward the positive supply voltage, resulting in a noticeably high level region. On the other hand, where an inductor current cycle""s turn-off signal to the power switching circuit""s lower switch occurs too early, the positive inductor current flows through the lower pass element""s body diode until it reaches zero amps, so that the phase voltage shown goes to a diode drop below ground before it transitions to the level of the output voltage.
A comparator produces an output signal used by the control logic to turn off the lower switch, in response to the contents of the digital counter matching the modified latch count. If the previous IL cycle""s turn-off signal to the power switching circuit""s lower switch occurred too late, the latched count value is decremented by one bit. This serves to effectively advance the time at which the output of the comparator changes statexe2x80x94by one period of the high frequency clock. If the previous IL cycle""s turn-off signal to the power switching circuit""s lower switch occurs early, the latched count value is incremented by one bit, so as to effectively delay the time at which the output of the comparator changes statexe2x80x94by one period of the high frequency clock.